Two-Way Training for Discriminatory Channel Estimation in Wireless MIMO Systems

This work examines the use of two-way training to efficiently discriminate the channel estimation performances at a legitimate receiver (LR) and an unauthorized receiver (UR) in a multiple-input multiple-output (MIMO) wireless system. This work improves upon the original discriminatory channel estimation (DCE) scheme proposed by Chang et al where multiple stages of feedback and retraining were used. While most studies on physical layer secrecy are under the information-theoretic framework and focus directly on the data transmission phase, studies on DCE focus on the training phase and aim to provide a practical signal processing technique to discriminate between the channel estimation performances at LR and UR. A key feature of DCE designs is the insertion of artificial noise (AN) in the training signal to degrade the channel estimation performance at UR. To do so, AN must be placed in a carefully chosen subspace based on the transmitter's knowledge of LR's channel in order to minimize its effect on LR. In this paper, we adopt the idea of two-way training that allows both the transmitter and LR to send training signals to facilitate channel estimation at both ends. Both reciprocal and non-reciprocal channels are considered and a two-way DCE scheme is proposed for each scenario. {For mathematical tractability, we assume that all terminals employ the linear minimum mean square error criterion for channel estimation. Based on the mean square error (MSE) of the channel estimates at all terminals,} we formulate and solve an optimization problem where the optimal power allocation between the training signal and AN is found by minimizing the MSE of LR's channel estimate subject to a constraint on the MSE achievable at UR. Numerical results show that the proposed DCE schemes can effectively discriminate between the channel estimation and hence the data detection performances at LR and UR.Comment: 1

Distributed timing analysis

As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly becoming the major bottleneck to the overall chip design closure process. To alleviate the long runtimes, recent trends are driving the need of distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this thesis, we introduce several methods to approach DTA problems. We present a near-optimal algorithm to speed up the path-based timing analysis in Chapter 1. Path-based timing analysis is a key step in the overall timing flow to reduce unwanted pessimism, for example, common path pessimism removal (CPPR). In Chapter 2, we introduce a MapReduce-based distributed Path-based timing analysis framework that can scale up to hundreds of machines. In Chapter 3, we introduce our standalone timer, OpenTimer, an open-source high-performance timing analysis tool for very large scale integration (VLSI) systems. OpenTimer efficiently supports (1) both block-based and path-based timing propagations, (2) CPPR, and (3) incremental timing. OpenTimer works on industry formats (e.g., .v, .spef, .lib, .sdc) and is designed to be parallel and portable. To further facilitate integration between timing and timing-driven optimizations, OpenTimer provides user-friendly application programming interface (API) for inactive analysis. Experimental results on industry benchmarks re- leased from TAU 2015 timing analysis contest have demonstrated remarkable results achieved by OpenTimer, especially in its order-of-magnitude speedup over existing timers. In Chapter 4 we present a DTA framework built on top of our standalone timer OpenTimer. We investigated into existing cluster computing frameworks from big data community and demonstrated DTA is a difficult fit here in terms of computation patterns and performance concern. Our specialized DTA framework supports (1) general design partitions (logical, physical, hierarchical, etc.) stored in a distributed file system, (2) non-blocking IO with event-driven programming for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines. In Chapter 5, we present our system DtCraft, a distributed execution engine for compute-intensive applications. Motivated by our DTA framework, DtCraft introduces a high-level programming model that lets users without detailed experience of distributed computing utilize the cluster resources. The major goal is to simplify the coding efforts on building distributed applications based on our system. In contrast to existing data-parallel cluster computing frameworks, DtCraft targets on high-performance or compute- intensive applications including simulations, modeling, and most EDA applications. Users describe a program in terms of a sequential stream graph associated with computation units and data streams. The DtCraft runtime transparently deals with the concurrency controls including work distribution, process communication, and fault tolerance. We have evaluated DtCraft on both micro-benchmarks and large-scale simulation and optimization problems, and showed the promising performance from single multi-core machines to clusters of computers

UNIVERSAL STATUS LIGHT

Typically, hardware devices, such as networking devices, include status indicators that display the status of ports and other elements related to the device. Each status indicator includes a status light that is carried by a plastic tube or pipe. Large amounts of plastic are typically involved in the manufacture of port status plastic tubes for networking devices worldwide. Techniques described herein provide for a universal status light that can be provided for networking devices in which the universal status light provides for merging port status indicators and general status indicators into a single status indicator, which may help to reduce plastic consumption and CO2 emissions